The present invention relates to Analog-to-Digital (AID) converters, and more particularly to parallel path A/D converters.
Analog-to-Digital (A/D) converters are widely used to convert an analog input signal to a multi-bit digital output signal. As is well known to those having skill in the art, a class of A/D converters is a parallel path A/D converter, also referred to herein as a multi-process A/D converter. In a parallel path A/D converter, a plurality of signal paths are responsive to an analog input signal, to generate a multi-bit digital signal therefrom. A respective signal path includes therein a comparator.
FIG. 1 illustrates an example of a conventional multi-process A/D converter. As shown in FIG. 1, the A/D converter receives an analog input signal SI from, for example, an external terminal, converts the received input signal into digital signals via multiple paths comprised of a plurality of process routines 102, 104 and 106, a plurality of comparators 108, 110 and 112, and a plurality of decoders 114, 116 and 118, and then generates an n-bit digital output signal DO[0:nxe2x88x921] therefrom.
A/D-converted digital signals PO1-PO(N) are generated from the plurality of comparators 108, 110 and 112 respectively connected to the process routines 102, 104 and 106. The A/D-converted digital signals PO1-PO(N) are compared and analyzed in a synchronizing circuit 122, so that synchronized signals CSO1 to CSO(N) are generated from the synchronizing circuit 122, and then applied to the decoders 114, 116 and 118 respectively corresponding to the process routines 102, 104 and 106. Digital output signals DO[0:ixe2x88x921]-DO[m:nxe2x88x921] generated from the decoders 114, 116 and 118, corresponding to the respective process routines, constitute the n-bit digital output signal DO[0:nxe2x88x921].
The analog input signal SI propagates with different time delays while passing through the different signal paths, having different signal distortions from one another. However, in the conventional A/D converter of FIG. 1, since the comparators 108, 110 and 112, the decoders 114, 116 and 118, and the synchronizing circuit 122 are controlled on respective paths by the same internal clock signal ICLK provided by a clock buffer 120, an erroneous conversion of the signals may occur, which may result in the generation of erroneous signals. The conventional synchronizing circuit 122 of FIG. 1 generally performs a latching function of synchronizing the output signals of the comparators to a clock signal, and a function of correcting the generated erroneous signals.
FIG. 2 is a block diagram illustrating an example of a conventional parallel path A/D converter with folding/interpolation and flash process routines. The A/D converter of FIG. 2 receives an analog input signal SI from, for example, an external terminal, converts the received signal SI into a digital signal via both paths of the folding/interpolation process routine 202 and the flash process routine 204, and then generates a digital output signal DO of a desired bit-number therefrom. Also, in the A/D converter of FIG. 2, the analog input signal SI propagates with different time delays while passing through the different signal paths, being distorted with different patterns from one another. However, in the conventional A/D converter of FIG. 2, since the comparators 206 and 208, the decoder 214 and the synchronizing circuit 212 are controlled on each path by the same internal clock signal ICLK provided by a clock buffer 210, an erroneous conversion of the signals may occur, which may result in the generation of erroneous signals. The conventional synchronizing circuit 212 of FIG. 2 compares the signals, which are input through different paths from each other, to synchronize them to the clock signal.
FIG. 3 is a timing diagram that illustrates a process of synchronization according to a synchronizing circuit of FIG. 2. FIG. 4 illustrates a synchronizing circuit of FIG. 2 using a logic circuit.
In FIG. 3, it is assumed that the Most Significant Bit (MSB) and the second most significant bit MSB-1 are a signal PO1 passing via the folding/interpolation process routine 202 and the comparator 206 of FIG. 2, and that the third most significant bit MSB-2 is a signal PO2 passing via the flash process routine 204 and the comparator 208. In FIG. 3, the MSB and the MSB-1 are synchronized to each other, but the MSB and the MSB-2, or the MSB-1 and the MSB-2 are not synchronized to each other. Accordingly, such asynchronous bit patterns may cause the converted digital signals to include code glitch errors. When synchronizing errors appearing at time points T3-T2 are present, it defines a time region A including the asynchronous time points T1-T4. Then, a synchronizing operation is performed for the region to be corrected by the synchronizing circuit as shown in FIG. 4.
In FIG. 4, it is assumed that the signal PO1 indicates the MSB, the signal PO2 indicates the MSB-2, and that the signal SA represents xe2x80x9c1xe2x80x9d within a range of the time region A while the signal SA represents xe2x80x9c0xe2x80x9d out of the range of the time region A. In synchronizing the MSB with the MSB-2, the MSB-2 is logically ORed with the MSB in the time region A after developing the same phase with the MSB by logic inversion. As a result of the OR operation, the MSB having an edge trigger later than the MSB-2 within the region A is synchronized to the MSB-2. Thus, the code glitch error can be corrected.
Unfortunately, it may be difficult to extend the range of error correction because the correcting region may be set for synchronization and the correcting region may be narrow. Furthermore, the conventional A/D converter may not conformably address the asynchronous signal, but may only correct the code glitch errors.
Some embodiments of the present invention provide an A/D converter that includes a plurality of signal paths that are responsive to an analog input signal, to generate a multi-bit digital signal therefrom. A respective signal path includes therein a comparator. A synchronizing circuit is responsive to a clock signal and outputs of the comparators, to generate a respective delayed clock signal that is applied to a respective comparator. In some embodiments, a respective signal path also includes therein a respective decoder that is responsive to a respective comparator and to the clock signal. In some embodiments, the synchronizing circuit is configured to generate a respective delay clock signal based on at least one phase difference between the outputs of the comparators.
Synchronizing methods according to some embodiments of the present invention may be used in A/D converters that include a plurality of signal paths that are responsive to an analog input signal, to generate a multi-bit digital signal therefrom, wherein a respective path includes therein a comparator. According to these methods, a plurality of delayed clock signals are generated from a clock signal and outputs of the comparators. A respective one of the delayed clock signals is applied to a respective comparator. In other embodiments, the clock signal is also applied to the respective decoders. In still other embodiments, the delayed clock signals are generated based on at least one phase difference between the outputs of the comparators.
Other embodiments of the present invention provide an A/D converter that comprises a clock buffer that is configured to receive and buffer an external clock signal, to thereby generate an internal clock signal. A plurality of process routines are configured to receive and process an analog input signal. The plurality of comparators are configured to receive analog signals from the plurality of process routines, and to compare the received analog signals with a reference voltage, to thereby generate digital signals therefrom, under control of a respective one of delayed clock signals. A plurality of decoders are configured to receive the digital signals from the plurality of comparators, and to convert the received digital signals into a code format, to thereby generate converted digital signals. A synchronizing circuit is configured to receive the internal clock signal from the clock buffer and the digital signals from the plurality of comparators, and to generate the respective delayed clock signals therefrom.
In still other embodiments, the synchronizing circuit includes a phase detector that is configured to receive the digital signals from the plurality of comparators and to detect a phase difference between the digital signals. A delay controller is configured to receive an output signal of the phase detector and to generate a respective time delay control signal for a respective one of the process routines, corresponding to the phase difference. A plurality of delay chain parts are configured to receive the internal clock signal from the clock buffer, and to generate the respective delayed clock signals, under control of a respective one of the time delay control circuits.